|Author||Ashok Srivastava and Saraju P. Mohanty|
|Category||Engineering and Technology|
The demand for ever smaller and more portable electronic devices has driven metal oxide semiconductor-based (CMOS) technology to its physical limit with the smallest possible feature sizes. This presents various size-related problems such as high power leakage, low-reliability, and thermal effects, and is a limit on further miniaturization. To enable even smaller electronics, various nano-devices including carbon nanotube transistors, graphene transistors, tunnel transistors and memristors (collectively called post-CMOS devices) are emerging that could replace the traditional and ubiquitous silicon transistor.
Over two volumes this work describes the modelling, design, and implementation of nano-scaled CMOS electronics, and the new generation of post-CMOS devices, at both the device and circuit levels.
Volume 1 explores these nano-electronics at the device level including modelling and design. Topics covered include high-K dielectric based devices; graphene transistors; high mobility n and p channels; anodic MIM capacitors; FinFET devices; reliability considerations of next-generation processors; timing driven buffer insertion for carbon nanotube interconnects; controllable-polarity nanowire transistors; carbon nanotubes for efficient power delivery; modelling of memristors at nanoscale; and neuromorphic devices.